Successive approximation register (SAR) type analog-to-digital (A/D) converters, which can be implemented by relatively simple circuit configurations, have excellent compatibility with CMOS processes and can be manufactured at relatively low cost, have recently been attracting attention as an A/D converter.
In semiconductor integrated circuits of a CMOS process, for example, when fabricating a successive approximation register type A/D converter, a scheme called as charge redistribution based on a switched capacitor technique is mainly employed. The reason is that a nearly ideal switch can be relatively easily implemented in a CMOS process.
An example of a conventional A/D converter and the operations thereof will be described referring to FIG. 1 to FIG. 3. FIG. 1 to FIG. 3 depict an example of a successive approximation register type A/D converter (SAR-ADC) described later in NPL 1 of [Citation List]. In FIG. 1 to FIG. 3, referential signs SA, SB, S4 to S0, and S0′ refer to switches, Vin refers to an analog input voltage, and Dout refers to a digital output (5 bits: b4 to b0).
FIG. 1 is a block diagram depicting an example of a conventional A/D converter and depicts 5-bit SAR-ADC based on charge redistribution using switched capacitor architecture. Capacitors each have a binary weighted value (capacitance: C, C/2, C/4, . . . , C/2n-1).
When all of the capacitors from capacitance C to the last two capacitors having the value C/2n-1 (C/16 in FIG. 1) are connected, i.e., when n+1 capacitors (six capacitors in FIG. 1) are connected, the total capacitance is 2C.
There are provided n+3 switches SA, SB, S4 to S0, and S0′ (eight switches in FIG. 1) for controlling the connections of the individual capacitors, and MOS-transistors are used for the switches. Switches SA, SB, S4 to S0, and S0′ are controlled so that the voltage comparator can provide the appropriate steering of the switches through auxiliary logic circuitry.
The conversion process is performed in three steps: the sample mode, the hold mode, and the redistribution mode (in which the actual conversion is performed). FIG. 2 is a diagram for depicting a sample operation and a hold operation in the A/D converter of FIG. 1, FIG. 2(a) depicts the sample operation (sample mode), and FIG. 2(b) depicts the hold operation (hold mode).
Firstly, as depicted in FIG. 2(a), in the sample mode, switch SA is closed and switch SB is switched to the input voltage Vin. The remaining switches S4 to S0, and S0′ are connected to the common bus B. Due to charging, a total charge of Qin=−2C×Vin is stored on the lower plates of the capacitors.
Next, as depicted in FIG. 2(b), in the hold mode, switch SA is opened while the switches S4 to S0, and S0′ are connected to ground, thereby applying a voltage of Vc=−Vin to the comparator input. This means that the circuit already has a built-in sample-and-hold element.
FIG. 3 is a diagram for depicting conversion step operations in the A/D converter of FIG. 1. FIG. 3(a) depicts the determination of the most significant bit (MSB; bit 4), FIG. 3(b) depicts the case when bit 4=1, and FIG. 3(c) depicts the case when bit 4=0.
The actual analog-to-digital conversion (A/D conversion), in which the analog input voltage Vin is converted to a digital signal, is performed by the (charge) redistribution mode. Firstly, the first conversion step, depicted in FIG. 3(a), connects C (the largest capacitor) via switch S4 to the reference voltage Vref, which corresponds to the full-scale range (FSR) of the A/D converter (ADC).
Capacitor C forms a 1:1 capacitance divider with the remaining capacitors connected to ground. The comparator input voltage is Vc=−Vin+Vref/2. When Vin>Vref/2, then Vc<0, and the comparator output goes up to the high level “1”, providing the most significant bit MSB (bit 4)=1. On the other hand, when Vin<Vref/2, then Vc>0, and the comparator output goes down to the low level “0”, providing bit 4=0.
As depicted in FIG. 3(b) and FIG. 3(c), the second conversion step connects C/2 to Vref. When the first conversion step resulted in bit 4=1, switch S4 is connected to ground again to discharge C, as depicted in FIG. 3(b).
On the other hand, as depicted in FIG. 3(c), when the first conversion step resulted in bit 4=0, switch S4 remains connected to Vref, resulting in a comparator input voltage of Vc=Vin+bit 4−Vref/2+Vref/4.
According to this voltage, the next most significant bit (bit 3) is obtained by comparing Vin to ¼ Vref or ¾ Vref through the different voltage dividers. In other words, switch S3 is either connected to ground when bit 3=1, thereby discharging C/2, or S3 remains connected to Vref when bit 3=0.
This process continues until all bits are generated, with the final conversion step being performed at a comparator input voltage of Vc=−Vin+bit 4×Vref/2 bit 3×Vref/4+bit 2×Vref/8+bit 1×Vref/16+bit 0×Vref/32.
The successive approximation register type A/D converter depicted in FIG. 1 to FIG. 3 is a single-ended circuit, and the present example is also applicable to differential A/D converters, as will be described in detail later.
As described above, the successive approximation register type A/D converter (SAR-ADC) includes a capacitive digital-to-analog (D/A) conversion unit disposed in the input unit thereof, thereby switching over switches SA, SB, S4 to S0, and S0′ among the sample mode, the hold mode, and charge redistribution mode.
Therefore, when the A/D conversion of the significant bit, especially, the A/D conversion of the most significant bit (MSB) is performed, it takes a long settling time because of a large amount of charge to be redistributed by the capacitive D/A conversion unit, resulting in the high probability of erroneous determination.
In other words, missing code, i.e., the state where some of the digital codes corresponding to the analog inputs are not output, may occur.
Patent Document 1: Japanese Laid-open Patent Publication No. 2003-283336
Non-Patent Document 1: Thomas KUGELSTADT, “Operations of Charge Redistribution type SAR-ADC,” JAJT017 (Japanese Translation of SLYT176), Texas Instruments Incorporated (Japanese version: Texas Instruments Japan Limited), pp. 1-4, November 2001, Searched Date: Nov. 9, 2013 Internet <URL: http://www.tij.co.jp/jp/lit/an/jajt017/jajt017.pdf>